Since my first engagement in counterfeit avoidance standards activity six years ago, I have on occasion heard concerns voiced about the use ‘mil-spec’ test methods for counterfeit detection. These concerns tend to surround commercial and industrial grade components where conditions for ‘environmental tests’ may exceed the use conditions specified by the device manufacturer. As one of the original developers of AS5553 and one who suggested the use of some of these ‘environmental tests’ for authenticity verification, I can share insight into the thinking behind the use of these methods and offer alternatives to ‘mil-spec’ test methods.
Revealing Disguises and Damage
When investigating counterfeit parts findings in the 2007 timeframe, my colleagues and I observed that a significant number of these cases involved parts that were used, but represented by the supplier as new and unused parts. Forensic analysis of these parts showed evidence of termination refurbishing and reclamation; many also exhibited other indications of counterfeiting. As my colleagues and I devised an authenticity verification (counterfeit detection) protocol, we selected tests that would reveal disguise techniques used by counterfeiters, but also tests we believed better suited to revealing defects from damage induced by abuse and contamination associated with counterfeiting operations – excessive heat, moisture, contaminants, electrostatic discharge and the combinational effects of these exposures. The tests and inspections we selected to reveal this sort of damage included electrical testing, thermal cycle testing, fine and gross leak testing (for hermetic devices), and burn-in. This authenticity verification process flow appears as ‘Figure E1’ within the original version of AS5553 (a specific process flow does not appear in AS5553A released 21 January).
Since we first devised this process flow, more sophisticated counterfeit detection methods have been developed in recent years, but, at the same time, counterfeiters continue to hone their craft to counter these methods. This can perpetuate the potential for parts to escape process flows that only include techniques designed to reveal disguises. Without applying tests to reveal damage associated with counterfeiting operations, escapes may occur that can affect performance in the end use application.
‘Mil-Spec’ vs. Industry Standard Test Methods
Tests such as thermal cycle testing, fine and gross leak testing, and burn-in (including electrical testing as acceptance criteria) are frequently associated with military standard test methods for ‘mil-spec’ parts. These tests are also defined by industry standards developed by semiconductor physics and packaging reliability subject matter experts to apply to commercial parts in conjunction with ongoing failure-mechanism-driven reliability monitoring. Elevated stresses are used to produce failure mechanisms observed under use conditions, but in a shorter time period. These elevated stresses can include exposure to higher and lower temperatures and higher moisture than would be associated with normal use conditions.
Research conducted by SEMATECH paved the way to reliability evaluation methods used today by the semiconductor manufacturing industry …
“Use Condition Based Reliability Evaluation of New Semiconductor Technologies,” SEMATECH Tech Transfer Document 99083810A-XFR, August 20, 1999
“Comparing the Effectiveness of Stress-based Reliability Qualification Stress Conditions,” SEMATECH Tech Transfer Document 04034510A-TR, April 12, 2004
JEDEC Publication JEP122G, “Failure Mechanisms and Models for Semiconductor Devices”
Industry standards defining tests currently used by the semiconductor industry include the ‘JEDEC Standards’, such as …
- JESD22-A101 Steady State Temperature Humidity Bias Life Test
- JESD22-A104 Temperature Cycling
- JESD22-A108 Temperature, Bias, and Operating Life
- JESD22-A110 Highly Accelerated Temperature and Humidity Stress Test (HAST)
Closing Remarks and Suggestions for Further Reading
As industry standards organizations seek to improve, refine and evolve authenticity verification (counterfeit detection) approaches, the design of test and inspection protocols could certainly incorporate the use of industry standard methods to reveal both disguises and damage. I acknowledge that the process flow I describe above is but one approach to revealing defects from damage induced by abuse and contamination associated with counterfeiting operations. If semiconductor physics and packaging reliability subject matter experts can devise an effective alternative that is also time and cost effective, I welcome it. I would also welcome approaches based on scientific research to help quantify the effects of this damage and to support equipment producers and DoD in risk management and in ‘Program Protection‘ activity as is applies to ‘counterfeit prevention’.
“Screening for Counterfeit Electronic Parts”, B. Sood, D. Das and M. Pecht, Journal of Materials Science: Materials in Electronics, Vol. 22, No. 10, pp. 1511-1522, 2011.
“Counterfeit Detection Strategies: When to Do It / How to Do It”, G. Caswell, DfR Solutions, March 2012.